1. Technical Field
The present invention relates to the communication of signals, in particular, to the transmission and reception of digital signals, where the signals are at a very high frequency.
The present invention is particularly applicable to interfaces between integrated circuits and for high speed communications, such as currently addressed by Asynchronous Transfer Mode (ATM), Gigabit Ethernet, SONET, 3GIO, RapidIO, Hyperchannel and Fibre Transmission Channels.
2. Background of the Invention
The input buffers to an integrated circuit comprise a series of open loop amplifiers, commonly of an inverting type (inverters). This means that the input signal need only switch a few millivolts around a voltage threshold, plus a noise margin, for the signal to switch logic states, the minimum Vil and Vih levels.
Transmission lines between integrated circuits are predominantly capacitive in their characteristic at very high frequencies. This means that to change state quickly, it is necessary to charge the line from a voltage source well above the Vih and to discharge the line to well below the Vil. It has been the practice to use saturating transistors which pull the line to a low value or drive it to a high value, then for this voltage to remain on the line until the next change is required.
In a digital system, the number of transitions in a pulse stream is normally much less than the clock frequency. The drive levels in a saturated system as described above mean that unless the signal changes polarity on the very next cycle, then the driver is storing energy on the line which must be discharged by the next transition.
The energy stored on a capacitor is QV/2 where Q is the charge in coulombs, or CV2/2. Thus, if there are f transitions a second, the energy required to drive a line is:E:=2f CV2/2
In a system where a line is driven to 1V for a high and 0V for a low, running at 10 GHz, with a line capacitance of 100 pF, then the energy required is 1 W, or 2 W for each differential pair.
Assuming a 20 mV noise window is required, and the switching threshold has a 6 mV hysteresis, then the energy actually needed to send the data is very much lower, as given by the equation:Ea:=2fC(V+0.016)2/2−2f C(V−0.016)2/2.
If the driver were to try to drive a signal from Vt+0.016V and Vt−0.016V then the signal would take many time constants to change state: in theory, an infinite number. Therefore to send the data, the driver must slew the signal at the required rate, and this means driving the capacitive loads from a higher voltage than is needed purely on threshold hysterisis and noise considerations alone.
The above consideration is effective and valid for low frequencies, where the signal is driving the whole transmission line up and down. At higher frequencies, the signal must drive that length of the line that is occupied by one bit: for example, assuming a propagation delay of 5.2 nS/m through a transmission line, then a system sending data at 190 MHz (380 Mbs) must charge and discharge one meter of transmission line on every bit change where the data is a clock signal. A typical coax cable has a capacitances that can vary from as low as 20 pF to as high as 200 pF/m. For example, Belden 8723 individually shielded twin twisted pairs have a capacitance of 203 pf/m core to cable+shield, whereas low capacitance RS485 cable is only 20 pF/m. More usually, cables are in the range 50 pF to 115 pF: for example TZC75024 75 Ohm telecom coaxial has a capacitance of 67 pF/m, RG58 A/U computer triax cable is 102 pf/m, 9903 Thin Ethernet cable is 114 pF/m, and Category 5 Belden 1583E unshielded twisted pair has a capacitance of 50 pF/m. Capacitances of pcb traces are usually in a similar range. These are very large values of capacitive loading for MOS drivers.
In high speed systems, the data is usually encoded, for example 8b/10b encoding is used to achieve a DC balanced code with a bit change every 16 bits. The newly invented 8b/13b codes and 8b/16b codes by the same inventors of the present invention described in UK 0202366.1 reduces the number of bit changes for any given channel bandwidth. For example the 8b/13b coding scheme gives a bit changes at less than ⅓rd of the data rate. In this case, the length of the line being charged or discharged is increased, compared to sending a pure clock signal, and this again increases the power consumption in linear proportion to the ratio of the frequency of bit interval changes to the clock frequency. Thus, as the frequency of communication increases, the amount of capacitance seen by the driver does not reduce linearly, but reduces as a the product of the linear reduction in the length of the line being driven by the bit and the increase in bit length that is an artifact of the coding.
Another factor in very high speed systems is that the driver must be differential: without this the currents injected into the power supplies and the radiated energy becomes excessive. The power supply noise created on switching is a critical factor in these systems. Differential drivers use a constant current source and arrange the switching to drive that same current into one of two lines forming a signal pair at all times. If the current in the differential driver is modulated then large amounts of noise can be injected into the power and ground rails. Attempts to reduce the power consumption of the line and driver combination must accommodate these currents if they are to be capable of effective implementation.
In order to drive a large capacitive load, the driver requires a predriver, which increases the electrical energy that can be driven, ideally by a factor of 3 or so per stage. The predriver can often consume more power than the driver when there is a heavily capacitive load due to the reflected Miller capacitance.
An attempt to solve the above problems was made in Jong et al., U.S. Pat. No. 6,518,792 disclosing a method and circuitry for pre-emphasizing transmitted logic signals. The idea was to configure a driver circuit may for monitoring the logic values of signals transmitted by the driver circuit and comparing the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal occurred based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals had the same logic value, and the next logic signal has a different value, the next logic value was pre-emphasized. If the next logic signal had a logic value that is equivalent to either the first logic signal or the second logic signal, it was transmitted without pre-emphasis.
A circuitry for embodying this method includes a driver circuit having selection logic, a pre-emphasis controller, and an output circuit. However, power savings obtained by using the method and circuitry of Jong et al. are insufficient.
Selection logic 51 includes monitoring circuit 52, comparison logic 54, and pre-emphasis controller 56. The next logic signal to be transmitted, A(n), is received by a shift register in monitoring circuit 52. The shift register of monitoring circuit 52 is configured to capture the logic value of A(n), as well as the logic values of A(n−1) and A(n−2). With each clock cycle, the logic values in the shift register shift one place in the shift register. Thus, the shift register of monitoring circuit is able to store the state of the A(n), A(n−1), and A(n−2) for any clock cycle.
Thus, it can be seen that in the circuitry of Jong et al. the length of pre-emphasized signal is dictated by the clock signal. This may be tolerable at relatively low-speeds; however, high-speed communications can require shorter pre-emphasized signals.
In the above context, long pre-emphasized signals do not match high-speed communications and obviously lead to excessive power consumption.